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MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
M66011FP M66011FP
SERIAL BUS CONTROLLER SERIAL BUS CONTROLLER
DESCRIPTION M66011 Semiconductor Integrated Circuit is a serial bus controller. It converts 2-byte parallel data that arrives from microcomputer into serial and outputs it to serial bus. It also converts serial data input from serial bus into parallel and outputs it to microcomputer. The M66011 is used for the extension of microcomputer I/O ports and two-way communication with peripheral equipment connected with serial buses. FEATURES * Compatible with general-purpose 8-bit microprocessor busses * TTL level input (one microcomputer side) * Interrupt output * Schmitt input (RESET, CS, SIN) * Low power dissipation * Wide operating temperature range (Ta = -20 to 75C) APPLICATION Microcomputer I/O port extension, etc.
PIN CONFIGURATION (TOP VIEW)
RESET INPUT RESET WRITE INPUT CHIP SELECT INPUT WR CS D0 D1 D2 DATA BUS D3 D4 D5 D6 D7 GND
1 2 3 4
24 23 22 21
VCC RD A0 A1 READ INPUT ADDRESS INPUT
M66011FP
5 6 7 8 9 10 11 12
20 19 18 17 16 15 14 13
SCLK SHIFT CLOCK OUTPUT SOUT SERIAL DATA OUTPUT SIN OE INT Xin Xout VCC SERIAL DATA INPUT OUTPUT ENABLE OUTPUT INTERRUPT OUTPUT CLOCK INPUT CLOCK OUTPUT
Outline 24P2N-B
BLOCK DIAGRAM
A1 21 RESET INPUT RESET 1 CHIP SELECT INPUT CS 3 WRITE INPUT WR 2 READ INPUT RD 23 Xin 15 Oscillation circuit CLOCK OUTPUT 14 Xout
Af 22 SHIFT CLOCK OUTPUT 20 SCLK
Timing control circuit CLK, LOAD Shift register for lower byte serial output (8 bits) SRL CLK, LOAD Shift register for upper byte serial output (8 bits) SRU
16 INT INTERRUPT OUTPUT 17 OE OUTPUT ENABLE OUTPUT
CLOCK INPUT
19 SOUT SERIAL DATA OUTPUT
DATA BUS
D0 D1 D2 D3 D4 D5 D6 D7
4 5 6 7 8 9 10 11
8
CLK Shift register for serial input (9 bits) 8 Read register Acknowledge bit (ACK) 8
18 SIN SERIAL DATA INPUT
8 X8
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
FUNCTION M66011 integrated circuit is a serial bus controller. It is equipped with two 8-bit shift registers used to convert parallel input data into serial for output, as well as with one 9-bit shift register used to convert serial input data into parallel for output. This IC receives and sends 8-bit parallel in communication with microcomputer. In communication with serial bus, it outputs 16-bit data and receives 9-bit data.
Serial data input/output uses four signal lines: shift clock output SCLK, serial data output SOUT, serial data input SIN and output enable output OE. Serial data is output synchronously with shift clock fall edges, while input of serial data is synchronous with shift clock rise edges. Serial communication data consists of one prefixed acknowledge bit and 8 data bits.
PIN DESCRIPTIONS
Pin RESET CS WR RD D0~D7 SCLK SOUT SIN OE INT A0, A1 Xin Xout VCC GND Name Reset input Chip select input Write input Read input Data bus Shift clock output Serial date output Serial data input Output enable output Interrupt output Address input Clock input Clock output Positive supply pin Grounding pin Input/Output Input Input Input Input Input/Output Output Output Input Output Output Input Input Output -- -- Functions "L" level: M66011 is reset to initial state. "L" level: M66011 becomes accessible. "L" level: 8-bit parallel data is input from data bus and written on M66011. "L" level: Serial-input 8-bit data or internal status data is output in parallel to data bus. Bi-directional 8-bit bus buffer. Used for communication with microcomputer (data write and read). Outputs clock to serial bus. Active ("H") status normally. Outputs serial data to serial bus. Active ("H") status normally. Inputs serial data from serial bus. "L" when serial data communication is executed. Active ("H") otherwise. Outputs interrupt command signal to microcomputer when serial data communication is finished. Selects register on which data is written during write operation. Designates data to be read during read operation. Connected to ceramic resonator, generates M66011 activation clock and SCLK output clock. If clock is input from outside, use pin Xin and keep pin Xout open. Connected positive supply (5V). Used for grounding (0V).
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
OPERATION 1. Write operation (1) Serial output data setting The M66011 has two built-in 8-bit shift registers. They are used to set serial output data. When the address setting is (A1, A0) = (0, 1), 8-bit data on data bus is written on the upper byte serial output shift register (SRU). When the address setting is (A1, A0) = (0, 0),
the data is written on the lower byte serial output shift register (SRL). In either case, data write starts when WR is on the "L" level. (2) Status register setting When the address setting is (A1, A0) = (1, 1), written data becomes the setting of status register in M66011. (Refer to the table below.)
Write Operation Basic Functions (Note 1)
CS 0 0 0 A1 0 0 1 A0 0 1 1 RD 1 1 1 WR 0 0 0 * Lower byte serial output shift register * Upper byte serial output shift register * Shift clock divider ratio register * Interrupt output control register Functions Data bus data Data bus data (Note 2) Data bus data
Note 1: Figure "0" indicates "L" level, while "1" indicates "H" level.
Note 2:
D7
D6
D5
D4
D3
D2
D1
D0
D1 0 0
D0 Divider ratio 0 1 0 1 1/2 1/4 1/8 1/16
Don't care
Don't care
1 1
"0": Interrupt output disable (INT output is fixed to "L".) "1": Interrupt output enable (INT output shifts from "L" to "H" when serial communication is completed.)
Write on SRU CS "L" or "H" WR Data buses D0~D7 D0U~D7U OE
Write on SRL
D0L~D7L
SOUT D7U~D0U SCLK Write Operation Basic Timing (Serial Output Data Setting) D7L~D0L
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
2. Read operation When a read access arrives, M66011 outputs data in parallel to data bus. The data output at this moment may be serial input data, or data on internal status resister. When a read access arrives when the address setting is (A1, A0) = (1, 0), 8-bits of 9-bit serial input data, excluding
the acknowledge bit, is output to data bus While RD is "L". When a read access arrives when the address setting is (A1, A0) =(1, 1), interrupt control register, busy flag, serialinput acknowledge bit and clock dividing ratio register are output to data bus while RD is "L".
Read Operation Basic Function
CS 0 0 A1 1 1 A0 0 1 RD 0 0 WR 1 1 Date bus Data bus Functions Serial input shift register Status register
Read Output Data Details (1) When (A1, A0) is (1, 0):
Data bus
D7
D6
D5
D4
D3
D2
D1
D0 Serial input data least significant bit (DI0) Serial input data most significant bit (DI7)
(2) When (A1, A0) is (1, 1):
Data bus
D7
D6
D5
D4
D3
D2
D1
D0 Shift clock dividing ratio
D1 0 0 1 1
D0 Divider ratio 0 1 0 1 1/2 1/4 1/8 1/16
Not specified
Acknowledge bit
Busy flag (Refer to 3, Serial data input/output operation for details.) "0": Access possible "1": Serial communication in progress. Write access prohibited. Interrupt control register data "0": Interrupt output disable "1": Interrupt output disable
CS
RD
Data buses D0~D7
VALID High impedance Read Operation Timing High impedance
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
3. Serial data input/output operation A cycle of 16-bit serial output data setting and serial data communication starts with a write access given by microcomputer to transmission shift registers in M66011. M66011 has two 8-bit shift registers, on for upper byte (SRU), the other for lower byte (SRL). If the CS status rises from "L" to "H" after a write access is given to SRL, serial data communication is started. SRU 8-bit data and SRL, 8bit data are output in series in this order. Output of each data starts from its most significant bit. At the CS rise edge, busy flag in M66011 is set, and OE output shifts from "H" to "L". Shift clock SCLK and serial data SOUT are then output. At SCLK fall edges, serial output shift register executes shifting operation, and data on shift register is output in series from pin SOUT. Serial input data from pin SIN is taken into input shift register at SCLK 8T thru 16T rise edges. However, data taken in at 8T rise edge is processed as acknowledge bit, while data taken in at 9T thru 16T rise edges are processed as data bits.
After the SCLK 16T rise edge, the status of SOUT and OE shifts to "H" after one bit's delay of SCLK, and busy flag is reset. When interrupt output is being set to enable, INT output is set. (Remarks) (1) If CS rises after write operation is executed on SRL only and not on SRU, SRU data is unstable. (2) When write operations executed on SRL, M66011 becomes ready for start of serial communication and stands by for detection of CS rise. However, if a read access is given after data is written on SRL while CS is maintained on "L" level, this standby status is canceled. To resume serial communication in this case, rewrite data on SRL and raise CS.
SRL write operation CS Busy flag (in M66011) OE INT
Serial communication period
SCLK 1T SOUT 2T 8T D08 9T D07 D06 D05 D04 D03 D02 D01 16T D00 (D0L) DI6 DI5 DI4 DI3 DI2 DI1 DI0
D015 D014 D013 D012 D011 D010 D09 (D7U)
(D0U) (D7L) ACK DI7
SIN
Serial Communication Timing Chart
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
4. Shift clock output Shift clock output pin (SCLK) outputs clock pulses generated by ceramic resonator oscillation circuit connected between pins Xin and Xout, or divided clock pulses input via pin Xin from external clock. The dividing ratio can be selected from among 1/2, 1/4, 1/8 and 1/16. 5. Interrupt output When interrupt output control register is set to "1" (interrupt output enable), the status of this output shifts from "L" to "H" at the end of a serial communication cycle, and an interrupt command is given to microcomputer. Interrupt output "H" is reset when read accessed. When interrupt output control register is set to "0" (interrupt output disable), the status of this output is retained on the "L" level. 6. Conditions when reset If "L" is input to RESET, M66011 are put under the conditions as specified below:
Pin name OE, SCLK and SOUT outputs Internal busy flag Acknowledge bit register INT output Divider ratio Status Active ("H") Reset ("L") Set ("H") Disable (continuous "L" output) 1/2
7. Oscillation circuit An example of circuit connection and circuit constants are given below for the case where a ceramic resonator is used.
M66011FP Xin Rf Ceramic resonator C1 C2 Xout
Clock Oscillation Circuit
Maker Ceramic resonator CSA4.00 MG 040 CST4.00 MGW 040 CSA8.00 MT CSA8.00 MTW Frequency (MHz) 4.0 4.0 8.0 8.0 C1 (pF) 100 100 (built-in) 30 30 (built-in) C2 (pF) 100 100 (built-in) 30 30 (built-in) Rf (M) 1.0 1.0 1.0 1.0
Murata Mfg.
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO Pd Tstg Parameter supply voltage Input voltage Output voltage Power dissipation Storage temperature Ratings -0.5 ~ +7.0 -0.5 ~ VCC + 0.5 -0.5 ~ VCC + 0.5 500 -60 ~ 150 Unit V V V mW C
RECOMMENDED OPERATIONAL CONDITIONS
Symbol VCC VI VO Topr Parameter Supply voltage Input voltage Output voltage Operating temperature Min. 4.5 0 0 -20 Limits Typ. 5.0 Max. 5.5 VCC VCC 75 Unit V V V C
ELECTRICAL CHARACTERISTICS (Ta = -20 ~ 75C, VCC = 5V 10% and GND = 0V unless otherwise noted)
Symbol VIH VIL VIH VIL VT+ VT- Vh VOH VOL II IOZ ICC CI/O Parameter "H" input voltage "L" input voltage "H" input voltage "L" input voltage Positive threshold voltage Negative threshold voltage Hysteresis width "H" output voltage "L" output voltage Input leak current Output leak current in off state Quiescent supply current Input/output pin capacitance WR, RD, A0, A1, D0~D7 Xin Test conditions Min. 2.0 VCCx0.8 VCCx0.2 2.4 RESET, CS, SIN 0.7 0.6 D0~D7, SCLK, INT, SOUT, OE IOH=-4mA IOL=4mA VI=0~VCC VO=0~VCC VI=VCC, GND output open D0~D7 VCC-0.8 0.4 10 10 200 20 Limits Typ. Max. 0.8 Unit V V V V V V V V V A A A pF
D0~D7
Note 3: Standard value measuring conditions: Ta = 25C and VCC =5V
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
TIMING CONDITIONS (Ta = -20 ~ 75C, VCC = 5V 10%, GND = 0V)
Symbol tc() tWH() tWL() tr() tf() tW(R) tW(W) tsu(CS-R) tsu(A-R) tsu(CS-W) tsu(A-W) tsu(D-W) th(R-CS) th(R-A) th(W-CS) th(W-A) th(W-D) tsu(SI-CK) th(CK-SI) tBUSY tWH(CS) Parameter Clock cycle Clock "H" pulse width Clock "L" pulse width Clock rise time Clock fall time Read pulse width Write pulse width Chip select setup time before read Address setup time before read Chip select setup time before write Address setup time before write Data setup time before write Chip select hold time after read Address hold time after read Chip select hold time after write Address hold time after write Data hold time after write Serial data setup time Serial data hold time Internal processing time after write Chip select "H" time at serial communication start up Test conditions Min. 120 Limits Typ. tc()/2 tc()/2 20 20 100 100 0 0 0 0 40 0 0 0 0 0 100 100 5tc() 5tc() Max. 520 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SWITCHING CHARACTERISTICS (Ta = -20 ~ 75C, VCC = 5V 10%, GND = 0V)
Symbol tPZH(R-D) tPZL(R-D) tPHZ(R-D) tPLZ(R-D) Parameter Data output enable time after read Data output disable time after read SCLK-SOUT OE-SCLK SCLK-OE CL=150pF RL=2K (Note 4) 5 Test conditions Min. Limits Typ. Max. 80 50 60 tc()+20 n * tc() 2 Unit ns ns ns ns ns
n: Divider ratio
tPLH, tPHL
Serial output propagation delay time
NOTE 4: TEST CIRCUIT
Symbol tPZH(R-D) tPZL(R-D) tPHZ(R-D) tPLZ(R-D) tPLH, tPHL S1 Open Closed Open Closed Open S2 Closed Open Closed Open Open
Input test point
VCC
Output test point
RL S1 CL 50 (2) S2 RL
(1) P.G.
Input
DUT
Output
(1) Pulse generator (PG) characteristics: tr=tf=6ns, Zo=50 (2) Capacitance CL includes connection floating capacitance and probe input capacitance.
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
TIMING CHARTS
Clock timing
tc() tWL() 50% 50% tWH() 90% 50% 10% tr() tf() 10% 90%
Read operation timing
tW(R) RD tsu(CS-R), tsu(A-R) CS, A0, A1 1.5V 1.5V th(R-CS), th(R-A)
1.5V
1.5V
tPZH(R-D), tPZL(R-D)
tPHZ(R-D), tPLZ(R-D) 90% 1.5V 10%
D0 ~ D7
Write operation timing
tW(W) WR tsu(CS-W), tsu(A-W) CS, A0, A1 1.5V 1.5V th(W-CS), th(W-A)
1.5V tsu(D-W) th(W-D)
1.5V
D0 ~ D7
1.5V
1.5V
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
Write operation internal processing time
tBUSY
WR
1.5V
1.5V
Serial input communication start timing
SRL Write access to SRL tWH(CS)
CS
1.5V
1.5V
Serial input operation
SCLK
1.5V
tsu (SI-CK)
th (CK-SI)
SIN
1.5V
1.5V
Serial output operation
SCLK
1.5V
tPLH, tPHL
SOUT
1.5V
OE
1.5V
1.5V
tPHL
tPLH
SCLK
1.5V
1.5V
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
Operation Flow Chart
Start
Start
Status register set
Status register set
SRU write
SRU write
SRL write
SRL write
CS="L" to "H" (Serial communication) Status read
CS="L" to "H" (Serial communication start) (Serial communication end) Interrupt command output
NO
Busy flag ="0" YES
Status read
NO
Acknowledge ="0" YES
NO
Acknowledge ="0" YES
Serial input data read
Serial input data read
Communication trouble
END
Communication trouble
END
When Busy Flag Is Used
When INT Output Is Used
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MITSUBISHI DIGITAL ASSP
M66011FP
SERIAL BUS CONTROLLER
APPLICATION EXAMPLE
SYSTEM RESET VCC or GND I/O-1 8
RESET RESET ADDRESS WR RD INT DATA BUS MICROCOMPUTER ADDRESS DECODER CS A0 A1 SCLK SOUT SIN OE
WR RD INT D0~D7 Xin Xout
RESET CLK A0~A4 DI DO D0~D7 EN M66009
M66011
RESET CLK A0~A4 DI DO D0~D7 EN M66009
VCC or GND I/O-2 8
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